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FEATURES AC PERFORMANCE 500 ns Settling to 0.01% for 10 V Step 1.5 s Settling to 0.0025% for 10 V Step 75 V/ s Slew Rate 0.0003% Total Harmonic Distortion (THD) 13 MHz Gain Bandwidth - Internal Compensation >200 MHz Gain Bandwidth (G = 1000) External Decompensation >1000 pF Capacitive Load Drive Capability with 10 V/ s Slew Rate - External Compensation DC PERFORMANCE 0.5 mV max Offset Voltage (AD744B) 10 V/ C max Drift (AD744B) 250 V/mV min Open-Loop Gain (AD744B) Available in Plastic Mini-DIP, Plastic SOIC, Hermetic Cerdip, Hermetic Metal Can Packages and Chip Form Surface Mount (SOIC) Package Available in Tape and Reel in Accordance with EIA-481A Standard APPLICATIONS Output Buffers for 12-Bit, 14-Bit and 16-Bit DACs, ADC Buffers, Cable Drivers, Wideband Preamplifiers and Active Filters PRODUCT DESCRIPTION
Precision, 500 ns Settling BiFET Op Amp AD744
CONNECTION DIAGRAMS TO-99 (H) Package
8-Lead Plastic Mini-DIP (N) 8-Lead SOIC (R) Package and 8-Lead Cerdip (Q) Packages
The AD744 is a fast-settling, precision, FET input, monolithic operational amplifier. It offers the excellent dc characteristics of the AD711 BiFET family with enhanced settling, slew rate, and bandwidth. The AD744 also offers the option of using custom compensation to achieve exceptional capacitive load drive capability. The single-pole response of the AD744 provides fast settling: 500 ns to 0.01%. This feature, combined with its high dc precision, makes it suitable for use as a buffer amplifier for 12-bit, 14-bit or 16-bit DACs and ADCs. Furthermore, the AD744's low total harmonic distortion (THD) level of 0.0003% and gain bandwidth product of 13 MHz make it an ideal amplifier for demanding audio applications. It is also an excellent choice for use in active filters in 12-bit, 14-bit and 16-bit data acquisition systems. The AD744 is internally compensated for stable operation as a unity gain inverter or as a noninverting amplifier with a gain of two or greater. External compensation may be applied to the AD744 for stable operation as a unity gain follower. External compensation also allows the AD744 to drive 1000 pF capacitive loads, slewing at 10 V/s with full stability. Alternatively, external decompensation may be used to increase the gain bandwidth of the AD744 to over 200 MHz at high
gains. This makes the AD744 ideal for use as ac preamps in digital signal processing (DSP) front ends. The AD744 is available in five performance grades. The AD744J and AD744K are rated over the commercial temperature range of 0C to +70C. The AD744A and AD744B are rated over the industrial temperature range of -40C to +85C. The AD744T is rated over the military temperature range of -55C to +125C and is available processed to MIL-STD-883B, Rev. C. The AD744 is available in an 8-lead plastic mini-DIP, 8-lead small outline, 8-lead cerdip or TO-99 metal can.
PRODUCT HIGHLIGHTS
1. The AD744 is a high-speed BiFET op amp that offers excellent performance at competitive prices. It outperforms the OPA602/OPA606, LF356 and LF400. 2. The AD744 offers exceptional dynamic response. It settles to 0.01% in 500 ns and has a 100% tested minimum slew rate of 50 V/s (AD744B). 3. The combination of Analog Devices' advanced processing technology, laser wafer drift trimming and well-matched ionimplanted JFETs provide outstanding dc precision. Input offset voltage, input bias current, and input offset current are specified in the warmed-up condition; all are 100% tested.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
AD744-SPECIFICATIONS
Model INPUT OFFSET VOLTAGE 1 Initial Offset Offset vs. Temp. vs. Supply2 vs. Supply Long-Term Stability INPUT BIAS CURRENT 3 Either Input Either Input @ T MAX = J, K A, B, C S, T Either Input Offset Current Offset Current @ T MAX = J, K A, B, C S, T FREQUENCY RESPONSE Gain BW, Small Signal Full Power Response Slew Rate, Unity Gain Settling Time to 0.01% 4 Total Harmonic Distortion INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential5 Common-Mode Voltage Over Max Operating Range 6 Common-Mode Rejection Ratio Conditions TMIN to TMAX
(@ +25 C and
Min Typ 0.3 5 95 15
15 V dc, unless otherwise noted)
AD744K/B/T
Max 1.0 2 20 88 88 Min Typ 0.25 5 100 15 100 2.3 6.4 102 150 50 1.1 3.2 52 9 50 0.75 30 0.7 1.9 31 40 10 0.2 0.6 10 13 1.2 75 0.5 100 2.3 6.4 102 150 50 1.1 3.2 52 Max 0.5 1.0 10 Unit mV mV V/C dB dB V/month pA nA nA nA pA pA nA nA nA MHz MHz V/s s
AD744J/A/S
TMIN to TMAX
82 82
VCM = 0 V VCM = 0 V 70C 85C 125C VCM = +10 V VCM = 0 V VCM = 0 V 70C 85C 125C G = -1 VO = 20 V p-p G = -1 G = -1 f = 1 kHz R1 2 k VO = 3 V rms 8 45
30 0.7 1.9 31 40 20 0.4 1.3 20 13 1.2 75 0.5
0.75
0.0003 3 3 1012||5.5 1012||5.5
0.0003 3 3 1012||5.5 1012||5.5
% ||pF ||pF V V V dB dB dB dB V p-p nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz V/mV V/mV V V mA pF V V mA
20 +14.5, -11.5 -11 VCM = 10 V TMIN to TMAX VCM = 11 V TMIN to TMAX 0.1 to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 1 kHz VO = 10 V RLOAD 2 k TMIN to TMAX RLOAD 2 k TMIN to TMAX Short Circuit Gain = -1 200 100 +13, -12.5 12 78 76 72 70 88 84 84 80 2 45 22 18 16 0.01 400 250 100 +13, -12.5 12 1000 15 3.5 +13 -11 82 80 78 74
20 +14.5, -11.5 +13 88 84 84 80 2 45 22 18 16 0.01 400
INPUT VOLTAGE NOISE
INPUT CURRENT NOISE OPEN LOOP GAIN 7
OUTPUT CHARACTERISTICS Voltage Current Capacitive Load8 POWER SUPPLY Rated Performance Operating Range Quiescent Current
+13.9, -13.3 +13.8, -13.1 25
+13.9, -13.3 +13.8, -13.1 25 1000 15 3.5
4.5
18 5.0
4.5
18 4.0
NOTES 1 Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = +25C. 2 PSRR test conditions: +VS = 15 V, -VS = -12 V to -18 V and +VS = +12 V to +18 V, -VS = -15 V. 3 Bias Current Specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25C. For higher temperature, the current doubles every 10C. 4 Gain = -1, RL = 2 k, CL = 10 pF, refer to Figure 25. 5 Defined as voltage between inputs, such that neither exceeds 10 V from ground. 6 Typically exceeding -14.1 V negative common-mode voltage on either input results in an output phase reversal. 7 Open-Loop Gain is specified with VOS both nulled and unnulled. 8 Capacitive load drive specified for CCOMP = 20 pF with the device connected as shown in Figure 32. Under these conditions, slew rate = 14 V/s and 0.01% settling time = 1.5 s typical. Refer to Table II for optimum compensation while driving a capacitive load. Specifications subject to change without notice. All min and max specifications are guaranteed.
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AD744
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 500 mW Input Voltage3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and -VS Storage Temperature Range (Q, H) . . . . . . -65C to +150C Storage Temperature Range (N, R) . . . . . . . -65C to +125C Operating Temperature Range AD744J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C AD744A/B . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C AD744S/T . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature Range (Soldering 60 seconds) . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics 8-Lead Plastic Package: JA = 100C/Watt, JC = 33C/Watt 8-Lead Cerdip Package: JA = 110C/Watt, JC = 22C/Watt 8-Lead Metal Can Package: JA = 150C/Watt, JC = 65C/Watt 8-Lead SOIC Package: JA = 160C/Watt, JC = 42C/Watt 3 For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage.
ORDERING GUIDE
Model AD744JN AD744KN AD744JR AD744KR AD744AQ AD744BQ AD744AH AD744JCHIPS AD744JR-REEL AD744JR-REEL 7 AD744KR-REEL AD744KR-REEL 7 AD744TA/883B
Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -55C to +125C
Package Option* N-8 N-8 SO-8 SO-8 Q-8 Q-8 H-08A Die Tape/Reel 13" Tape/Reel 7" Tape/Reel 13" Tape/Reel 7" H-08
*N = Plastic DIP; SO = Small Outline IC; Q = Cerdip; H = TO-99 Metal Can.
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions. Dimensions shown in inches and (mm).
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AD744 -Typical Characteristics
Figure 1. Input Voltage Swing vs. Supply Voltage
Figure 2. Output Voltage Swing vs. Supply Voltage
Figure 3. Output Voltage Swing vs. Load Resistance
Figure 4. Quiescent Current vs. Supply Voltage
Figure 5. Input Bias Current vs. Temperature
Figure 6. Output Impedance vs. Frequency
Figure 7. Input Bias Current vs. Common-Mode Voltage
Figure 8. Short Circuit Current Limit vs. Temperature
Figure 9. Gain Bandwidth Product vs. Temperature
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AD744
Figure 10. Open-Loop Gain and Phase Margin vs. Frequency CCOMP = 0 pF
Figure 11. Open Loop Gain and Phase Margin vs. Frequency CCOMP = 25 pF
Figure 12. Open-Loop Gain vs. Supply Voltage
Figure 13. Common-Mode and Power Supply Rejection vs. Frequency
Figure 14. Large Signal Frequency Response
Figure 15. Output Swing and Error vs. Settling Time
Figure 16. Total Harmonic Distortion vs. Frequency, Circuit of Figure 20 (G = 10)
Figure 17. Input Noise Voltage Spectral Density
Figure 18. Slew Rate vs. Input Error Signal
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AD744 -Typical Characteristics
Figure 19. Settling Time vs. Closed Loop Voltage Gain
Figure 20. THD Test Circuit
Figure 21. Offset Null Configuration
Figure 22a. Unity-Gain Follower
Figure 22b. Unity-Gain Follower Large Signal Pulse Response, CCOMP = 5 pF
Figure 22c. Unity-Gain Follower Small Signal Pulse Response, CCOMP = 5 pF
Figure 23a. Unity-Gain Inverter
Figure 23b. Unity-Gain Inverter Large Signal Pulse Response, CCOMP = 5 pF
Figure 23c. Unity-Gain Inverter Small Signal Pulse Response, CCOMP = 0 pF
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AD744
POWER SUPPLY BYPASSING
The power supply connections to the AD744 must maintain a low impedance to ground over a bandwidth of 10 MHz or more. This is especially important when driving a significant resistive or capacitive load, since all current delivered to the load comes from the power supplies. Multiple high quality bypass capacitors are recommended for each power supply line in any critical application. A 0.1 F ceramic and a 1 F electrolytic capacitor as shown in Figure 24 placed as close as possible to the amplifier (with short lead lengths to power supply common) will assure adequate high frequency bypassing, in most applications. A minimum bypass capacitance of 0.1 F should be used for any application.
+VS 1F
0.1 F
The error signal is thus clamped twice: once to prevent overloading amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. A Tektronix oscilloscope preamp type 7A26 was carefully chosen because it recovers from the approximately 0.4 V overload quickly enough to allow accurate measurement of the AD744's 500 ns settling time. Amplifier A2 is a very high-speed FET-input op amp; it provides a voltage gain of 10, amplifying the error signal output of the AD744 under test.
AD744
1F -VS
0.1 F
Figure 24. Recommended Power Supply Bypassing
MEASURING AD744 SETTLING TIME
The photos of Figures 26 and 27 show the dynamic response of the AD744 while operating in the settling time test circuit of Figure 25. The input of the settling time fixture is driven by a flat-top pulse generator. The error signal output from the false summing node of A1, the AD744 under test, is clamped, amplified by op amp A2 and then clamped again.
TO TEKTRONIX 7A26 1M OSCILLOSCOPE PREAMP INPUT SECTION (VIA LESS THAN 1 FT 50 COAXIAL CABLE) VERROR 206 2X HP2835 0.47 F +VS 0.47 F -VS 10k 1.1k 0.2pF - 0.8pF NULL 4.99k 200 4.99k 10k
Figure 26. Settling Characteristics 0 to +10 V Step Upper Trace: Output of AD744 Under Test (5 V/div.) Lower Trace: Amplified Error Voltage (0.01%/div.)
+15V COM -15V
+VS
20pF
-VS
5pF
10
2X HP2835
A2 AD3554
Figure 27. Settling Characteristics 0 to -10 V Step Upper Trace: Output of AD744 Under Test (5 V/div.) Lower Trace: Amplified Error Voltage (0.01%/div.)
FLAT-TOP PULSE GENERATOR
5pF - 18pF VIN 10k
AD744 A1
DATA DYNAMICS 5109 OR EQUIVALENT
5k +VS 1F 0.1 F -VS 1F
10pF
0.1 F
NOTE: USE CIRCUIT BOARD WITH GROUND PLANE
Figure 25. Settling Time Test Circuit
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AD744
EXTERNAL FREQUENCY COMPENSATION
Even though the AD744 is useable without compensation in most applications, it may be externally compensated for even more flexibility. This is accomplished by connecting a capacitor between Pins 5 and 8. Figure 28, a simplified schematic of the AD744, shows where this capacitor is connected. This feature is useful because it allows the AD744 to be used as a unity gain voltage follower. It also enables the amplifier to drive capacitive loads up to 2000 pF and greater.
+VS 400 A 300 -IN NULL / COMPENSATION NULL / DECOMPENSATION 1k 1k 8k -VS 300 +IN 5pF 2mA
The following section provides tables to show what C COMP values will provide the necessary compensation for given circuit configurations and capacitive loads. In each case, the recommended C COMP is a minimum value. A larger CCOMP can always be used, but slew rate and bandwidth performance will be degraded. Figure 30 shows the AD744 configured as a unity gain voltage follower. In this case, a minimum compensation capacitor of 5 pF is necessary for stable operation. Larger compensation capacitors can be used for driving larger capacitive loads. Table I outlines recommended minimum values for CCOMP based on the desired capacitive load. It also gives the slew rate and bandwidth that will be achieved for each case.
+VS
OUTPUT
1F 0.1 F
AD744
COMPENSATION
VIN CCOMP 5pF
VOUT
1F
0.1 F
Figure 28. AD744 Simplified Schematic
-VS
The slew rate and gain bandwidth product of the AD744 are inversely proportional to the value of the compensation capacitor, C COMP. Therefore, when trying to maximize the speed of the amplifier, the value of CCOMP should be minimized. CCOMP can also be used to slow the amplifier to a point where the slew rate is perfectly symmetrical and well controlled. Figure 29 summarizes the effect of external compensation on slew rate and bandwidth.
20 100
Figure 30. AD744 Connected as a Unity Gain Voltage Follower
Table I. Recommended Values of C COMP vs. Various Capacitive Loads
Gain 1 1 1
Max CLOAD (pF) 50 150 2000
CCOMP (pF) 5 10 25
Slew Rate (V/ s) 37 25 12.5
-3 dB Bandwidth (MHz) 6.5 4.3 2.0
GAIN BANDWIDTH - MHz
2
10
SLEW RATE - V/ s
0.2
1.0
Figures 31 and 32 show the AD744 as a voltage follower with gain and as an inverting amplifier. In these cases, external compensation is not necessary for stable operation. However, compensation may be applied to drive capacitive loads above 50 pF. Table II gives recommended CCOMP values, along with expected slew rates and bandwidths for a variety of load conditions and gains for the circuits in Figures 31 and 32.
CLEAD* R1* +VS 1F 0.1 F R2*
0.02 0 10 CCOMP - pF 100
0.1 1000
Figure 29. Gain Bandwidth and Slew Rate vs. CCOMP
AD744
VIN
VOUT OPTIONAL CCOMP 1F 0.1 F
*SEE TABLE II
-VS
Figure 31. AD744 Connected as a Voltage Follower Operating at Gains of 2 or Greater
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AD744
Table II. Recommended Values of C COMP vs. Various Load Conditions for the Circuits of Figures 31 and 32.
R1 () 4.99 k 4.99 k 4.99 k 4.99 k 499 499 499
R2 () 4.99 k 4.99 k 4.99 k 4.99 k 4.99 k 4.99 k 4.99 k
Gain Follower 2 2 2 2 11 11 11
Gain Inverter 1 1 1 1 10 10 10
Max CLOAD (pF) 50 150 1000 >2000 270 390 1000
CCOMP (pF) 0 5 20 25 0 2 5
CLEAD (pF) 7 7 - - - - -
Slew Rate (V/ s) 75 37 14 12.52 75 50 372
-3 dB Bandwidth (MHz) 2.51 2.31 1.2 1.0 1.2 0.85 0.60
NOTES 1 Bandwidth with C LEAD adjusted for minimum settling time. 2 Into large capacitive loads the AD744's 25 mA output current limit sets the slew rate of the amplifier, in V/ s, equal to 0.025 amps divided by the value of C LOAD in F. Slew rate is specified into rated max C LOAD except for cases marked 2, which are specified with a 50 pF. load.
CLEAD* R2* +VS R1* VIN 1F 0.1 F
Due to manufacturing variations in the value of the internal C COMP , it is recommended that the amplifier's response be optimized for the desired gain by using a 2 to 10 pF trimmer capacitor rather than using a fixed value.
R1* R2* +VS 1F 0.1 F
AD744
OPTIONAL CCOMP *SEE TABLE II 1F -VS 0.1 F
VOUT
AD744
VOUT NOT CONNECTED 2 - 10pF *SEE TABLE III
Figure 32. AD744 Connected as an Inverting Amplifier Operating at Gains of 1 or Greater
Using Decompensation to Extend the Gain Bandwidth Product
\
VIN
1F -VS
0.1 F
When the AD744 is used in applications where the closed-loop gain is greater than 10, gain bandwidth product may be enhanced by connecting a small capacitor between Pins 1 and 5 (Figure 33). At low frequencies, this capacitor cancels the effects of the chip's internal compensation capacitor, CCOMP, effectively decompensating the amplifier.
Figure 33. Using the Decompensation Connection to Extend Gain Bandwidth
Table III. Performance Summary for the Circuit of Figure 33
R1 () 1k 100 100
R2 ()
Gain Follower
Gain Inverter 10 100 1000
-3 dB Bandwidth 2.5 MHz 760 kHz 225 kHz
Gain/BW Product 25 MHz 76 MHz 225 MHz
10 k 11 10 k 101 100 k 1001
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AD744
REF OUT GAIN ADJUST 100 REF IN REF GND VCC 0.1 F 100 BIPOLAR OFFSET ADJUST
20V SPAN 10V 19.95k
AD565A
9.96k
5k 10V SPAN 5k DAC OUT
CLEAD 10pF +15V 1F
20k
8k
AD744
1F
0.1 F -VEE
POWER GND
MSB
LSB
-15V
Figure 34. 10 V Voltage Output Bipolar DAC Using the AD744 as an Output Buffer
HIGH-SPEED OP AMP APPLICATIONS AND TECHNIQUES DAC Buffers (I-to-V Converters) A HIGH-SPEED, 3 OP AMP INSTRUMENTATION AMPLIFIER CIRCUIT
Digital-to-analog converters which use bipolar transistors to switch currents into (or out of) their outputs can achieve very fast settling times. The AD565A, for example, is specified to settle to 12 bits in less than 250 ns, with a current output. However, in many applications, a voltage output is desirable, and it would be useful - perhaps essential - that this I-to-V conversion be accomplished without increasing the settling time or without degrading the accuracy of the DAC. Figure 34 is a schematic of an AD565A DAC using an AD744 output buffer. The 10 pF CLEAD capacitor compensates for the DAC's output capacitance, plus the 5.5 pF amplifier input capacitance. Figure 35 is an oscilloscope photo of the AD744's output voltage with a +10 V to 0 V step applied; this corresponds to an all "1s" to all "0s" code change on the DAC. Since the DAC is
The instrumentation amplifier circuit shown in Figure 36 can provide a range of gains from unity up to 1000 and higher. The circuit bandwidth is 4 MHz at a gain of 1 and 750 kHz at a gain of 10; settling time for the entire circuit is less than 2 s to within 0.01% for a 10 V step, (G = 10). While the AD744 is not stable with 100% negative feedback (as when connected as a standard voltage follower), phase margin and therefore stability at unity gain may be increased to an acceptable level by placing the parallel combination of a resistor and a small lead capacitor between each amplifier's output and its inverting input terminal. The only penalty associated with this method is a small bandwidth reduction at low gains. The optimum value for CLEAD may be determined from the graph of Figure 41. This technique can be used in the circuit of Figure 36 to achieve stable operation at gains from unity to over 1000.
CIRCUIT GAIN = 20,000 +1 RG *1.5pF - 20pF (TRIM FOR BEST SETTLING TIME) **10k **10k **10k 10k 5pF **10k A3 SENSE
AD744
-IN A1 10k 7.5pF RG 7.5pF
AD744
A2 +IN
REFERENCE
Figure 35. Upper Trace: AD744 Output Voltage for a +10 V to 0 V Step, Scale: 5 mV/div. Lower Trace: Logic Input Signal, Scale: 5 V/div.
AD744
*VOLTRONICS SP20 TRIMMER CAPACITOR OR EQUIVALENT **RATIO MATCHED 1% METAL FILM RESISTORS +15V 1F COMM 1F -15V -VS 1F 0.1 F PIN 4 +VS 1F 0.1 F PIN 7 EACH AMPLIFIER
connected in the 20 V span mode, 1 LSB is equal to 4.88 mV. Output settling time for the AD565/AD744 combination is less than 500 ns to within a 2.44 mV, 1/2 LSB error band.
FOR OPTIONAL OFFSET ADJUSTMENT: TRIM A1, A3 USING TRIM PROCEDURE SHOWN IN FIGURE 21.
Figure 36. A High Performance, 3 Op Amp Instrumentation Amplifier Circuit
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AD744
Table IV. Performance Summary for the 3 Op Amp Instrumentation Amplifier Circuit
Gain 1 2 10 100
RG NC 20 k 2.22 k 202
Bandwidth 3.5 MHz 2.5 MHz 1 MHz 290 kHz
T Settle (0.01%) 1.5 s 1.0 s 2 s 5 s
Equation 1 would completely describe the output of the system if not for the op amp's finite slew rate and other nonlinear effects. Even considering these effects, the fine scale settling to <0.1% will be determined by the op amp's small signal behavior. Equation 1.
VO -R = I IN R (CL + CX ) 2 GN s + + R CL s + 1 2FO 2FO
Where FO = the op amp's unity gain crossover frequency
R GN = the "noise" gain of the circuit 1 + RO
This Equation May Then Be Solved for CL: Equation 2.
CL = 2 RC X 2FO + (1 - GN ) 2 - GN + R 2FO R 2FO
Figure 37. The Pulse Response of the 3 Op Amp Instrumentation Amplifier. Gain = 1, l Horizontal Scale: 0.5 V/div., Vertical Scale: 5 V/div. (Gain= 10)
In these equations, capacitance CX is the total capacitance appearing at the inverting terminal of the op amp. When modeling an I-to-V converter application, the Norton equivalent circuit of Figure 39 can be used directly. Capacitance CX is the total capacitance of the output of the current source plus the input capacitance of the op amp, which includes any stray capacitance at the op amp's input.
CCOMP (OPTIONAL)
AD744
RL R IO RO CX CL CLOAD
VOUT
Figure 38. Settling Time of the 3 Op Amp Instrumentation Amplifier. Horizontal Scale: 500 ns/div., Vertical Scale, Pulse Input: 5 V/div., Output Settling: 1 mV/div.
Minimizing Settling Time in Real-World Applications
Figure 39. A Simplified Model of the AD744 Used as a Current-to-Voltage Converter
An amplifier with a "single pole" or "ideal" integrator open-loop frequency response will achieve the minimum possible settling time for any given unity-gain bandwidth. However, when this "ideal" amplifier is used in a practical circuit, the actual settling time is increased above the minimum value because of added time constants which are introduced due to additional capacitance on the amplifier's summing junction. The following discussion will explain how to minimize this increase in settling time by the selection of the proper value for feedback capacitor, CL. If an op amp is modeled as an ideal integrator with a unity gain crossover frequency, fO, Equation 1 will accurately describe the small signal behavior of the circuit of Figure 39. This circuit models an op amp connected as an I-to-V converter.
When RO and IO are replaced with their Thevenin VIN and RIN equivalents, the general purpose inverting amplifier model of Figure 40 is created. Here capacitor CX represents the input capacitance of the AD744 (5.5 pF) plus any stray capacitance due to wiring and the type of IC package employed.
CCOMP (OPTIONAL)
AD744
RL RIN VIN CX CL R
VOUT CLOAD
Figure 40. A Simplified Model of the AD744 Used as an Inverting Amplifier
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AD744
VALUE OF CAPACITOR CLEAD - pF
GN = 1.5 15 10 5 IN THIS REGION CLEAD = 0pF GN = 1 TO 0 100 GN = 2 GN = 3 1k 10k VALUE OF RESISTOR - 100k
As an aid to the designer, the optimum value of CL for one specific amplifier connection can be determined from the graph of Figure 41. This graph has been produced for the case where the AD744 is connected as in Figures 39 and 40 with a practical minimum value for CSTRAY of 2 pF and a total CX value of 7.5 pF. The approximate value of CL can be determined for almost any application by solving Equation 2. For example, the AD565/ AD744 circuit of Figure 34 constrains all the variables of Equation 2 (GN = 3.25, R = 10 k, FO = 13 MHz, and CX = 32.5 pF) Therefore, under these conditions, CL= 10.5 pF.
Figure 41. Practical Values of CL vs. Resistance of R for Various Amplifier Noise Gains
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
TO-99 (H) Package
0.185 (4.70) 0.165 (4.19) REFERENCE PLANE 0.5 (12.70) MIN 0.370 (9.40) 0.335 (8.50) 0.335 (8.50) 0.305 (7.75) 45 EQUALLY SPACED 1 8 7 0.04 (1.0) MAX INSULATION 0.05 (1.27) MAX 8 LEADS 0.019 (0.48) DIA 0.034 (0.86) 0.016 (0.41) 0.028 (0.71) SEATING PLANE 0.045 (1.1) 0.020 (0.51) BOTTOM VIEW 6 3 2 4 5 0.2 (5.1) TYP
Cerdip (Q) Package
0.005 (0.13) MIN
8
0.055 (1.35) MAX
5
PIN 1
1 4
0.310 (7.87) 0.220 (5.59)
0.1 (2.54) BSC 0.405 (10.29) MAX 0.20 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.06 (1.52) 0.015 (0.38) 0.15 (3.81) MIN 15 0 0.015 (0.38) 0.008 (0.20) 0.32 (8.13) 0.29 (7.37)
SEATING 0.023 (0.58) 0.07 (1.78) PLANE 0.014 (0.36) 0.03 (0.76)
Mini-DIP (N) Package
0.39 (9.91) MAX
8 5
Small Outline (SO-8) Package
PRINTED IN U.S.A.
0.033 (0.83 0.017 0.43) 0.193 (4.90 0.008 0.10)
0.31 (7.87)
1 4
0.25 (6.35)
8
5 4
0.154 (3.91
0.004 0.10) PIN 1
1
0.236 (6.00
0.012 0.20)
PIN 1 0.165 0.01 (4.19 0.25) 0.125 (3.18) MIN 0.018 (0.46
0.10 (2.54) TYP
0.30 (7.62) REF 0.035 0.01 (0.89 0.25)
0.008 (0.203
0.004 0.075)
0.050 (1.27) BSC 0.098 (2.49 0.017 (0.42 0.003 0.07) 0.006 0.23) 0.011 0.002 (0.269 0.03)
0.18 (4.57 0.003 0.08) 0.033 (0.84) NOM SEATING PLANE
0.03 0.76) 0-15 0.011 (0.28 0.003 0.08)
SEATING PLANE
-12-
REV.C
C00833a-0-7/00 (rev. C)
In either case, the capacitance CX causes the system to go from a one-pole to a two-pole response; this additional pole increases settling time by introducing peaking or ringing in the op amp's output. If the value of CX can be estimated with reasonable accuracy, Equation 2 can be used to choose the correct value for a small capacitor, CL, which will optimize amplifier response. If the value of CX is not known, CL should be a variable capacitor.
35 30 GN = 1 25 20

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